The present invention relates generally to an integrated circuit (xe2x80x9cICxe2x80x9d). More specifically, this invention relates to the fabrication of an integrated circuit having an improved polysilicon upper surface, by providing for an approximate planarization of this upper surface.
The present invention applies particularly to the fabrication of non-volatile memory integrated circuits. Some examples of non-volatile memory integrated circuits include an EPROM, an EEPROM, a flash memory device, and a complementary metal oxide silicon (xe2x80x9cCMOSxe2x80x9d) type device. An exemplary device may comprise a field-effect transistor (xe2x80x9cFETxe2x80x9d) containing a metal gate over thermal oxide over silicon (xe2x80x9cMOSFETxe2x80x9d), as well as other ultra-large-scale integrated-circuit (xe2x80x9cULSIxe2x80x9d) systems.
Non-volatile memory integrated circuits are utilized in a wide variety of commercial and military electronic devices, including, e.g., hand held telephones, radios and digital cameras. The market for these electronic devices continues to demand devices with a lower voltage, a lower power consumption and a decreased chip size. Also, the demand for greater functionality is driving the xe2x80x9cdesign rulexe2x80x9d lower, for example, into the sub-half micron range. The sub-half micron range may comprise, e.g., decreasing from a 0.35-0.25 micron technology to a 0.18 micron or a 0.15 micron technology, or even lower.
A portion of a conventional flash memory cell that comprises a flash memory IC is illustrated in FIG. 1. In referring to FIG. 1, a portion of a conventional flash memory cell fabrication process is described. It is understood by one skilled in the art that FIG. 1 is oriented such that the view is parallel to a word line.
FIG. 1 illustrates a cross-sectional view of the single flash memory cell 10 that is comprised of a conventional substrate 20. However, the respective source and drain regions are not shown. Axe2x80x2 tunnel oxide (xe2x80x9cToxxe2x80x9d) layer 30 is formed over the upper substrate portion 22, over which is formed a first polysilicon layer 44. The polysilicon layer 44 may be patterned, for example, by masking and etching. Next, an interpoly dielectric layer 52, e.g., Oxide Nitride Oxide (xe2x80x9cONOxe2x80x9d), is formed over the first polysilicon layer 44. Then, a second polysilicon layer 61 is formed upon the interpoly dielectric layer 52. Finally, a conventional silicide layer 80 is formed upon the second polysilicon layer 61.
The memory device illustrated in FIG. 1 utilizes the first polysilicon layer 44 as a floating gate in order to store a data element. The floating gate is controlled by the second polysilicon layer 61 that functions as a control gate.
Specifically, in forming the second polysilicon layer 61 as shown in FIG. 1, a number of depressions 65 and crevices 67 are formed in an upper portion of the second polysilicon layer 61. Then, when the silicide layer 80 is deposited upon an upper portion of the second polysilicon layer 61, the silicide layer 80 adopts at least a portion of the depressions 65 and crevices 67 so as to form word line voids 85 and word line seams 87.
These word line voids 85 and seams 87 often substantially increase the word line resistance. Because the word line resistance is increased by these word line voids 85 and seams 87, the word line resistance increases as the design rule continues to shrink, respectively.
In addition, the deposition of the second polysilicon layer 61 is one of the most critical and difficult lithography design rule problems, because of the difficulty of the gate masking of the second polysilicon layer 61. After the second polysilicon layer 61 deposition is completed, the topography of the upper surface of the second polysilicon layer 61 is often severe enough to detrimentally impact the feature definition by photolithography. Further, the depressions 65 and crevices 67 result in a relatively poor silicide formation. Thus, the conventional method results in an ever deteriorating performance as the design rule continues to shrink.
What is needed is a device and method for improving the ability to form a second polysilicon layer to the design rule with less difficulty. What is also needed is a device and method for improving the ability to form a second polysilicon layer with a reduced and/or eliminated amount and/or severity of depressions and crevices that are conventionally formed in an upper portion of the second polysilicon layer. Finally, what is needed is a device and method for improving the ability to form a silicide layer with a reduced and/or eliminated amount and/or severity of word line voids and seams that are conventionally formed in an upper portion of the silicide layer.
Embodiments of the present invention are best understood by examining the detailed description and the appended claims with reference to the drawings. However, a brief summary of embodiments of the present invention follows.
Briefly described, an embodiment of the present invention comprises a device and a method that provides for an improved polysilicon layer upper surface. This improvement is achieved by approximately planarizing an upper surface of the second polysilicon layer that is adjacent the silicide layer.
First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then, a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this removal achieves a relatively, or approximately, planarized upper surface of the polysilicon layer. Then, for example, a conventional metal layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for the silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.
Other arrangements and modifications will be understood by examining the detailed description and the appended claims with reference to the drawings.